The problems with traditional EDNMOS transistors are mainly related to high electrical field crowding at the edge of the channel due to nitride spacers acting as the sinker of charge spreading, which accelerates hot carrier injection (HCl) degradation. A known approach to improve the HCl performance of an EDNMOS is depicted in FIG. 1. Adverting to FIG. 1 (a cross-sectional view), a P-type well (p-well) 101 and an N-type drift or drain extension region (N−) 103 are formed in a substrate 105. A polysilicon gate 107 having a gate oxide layer 109 and nitride spacers 111 is formed across the p-well 101 and N− 103 regions. A silicide blocked (SBLK) layer 113 is then formed over one of the spacers 111. Next, a P+ region 115 is formed in the P-well 101 and N+ regions 117 are formed in the P-well 101 and N− 103 regions, respectively. Thereafter, a metal field plate is formed over a shallow trench isolation (STI) region formed over the substrate 105 (both not shown for illustrative convenience). High electrical field crowding; however, still occurs at the edge of the channel (as depicted by the arrows 119) since the nitride spacers 111 still act as the sinker of charge spreading. In addition, a metal field plate does not work well for thick dielectric layers in complimentary metal-oxide-semiconductor (CMOS) processing.
Another known approach attempts to address this problem by replacing the nitride spacers 111 of FIG. 1 with polysilicon spacers. However, forming polysilicon spacers requires an additional mask, which is costly. A further known approach employs a polysilicon field plate instead of the metal field plate. However, the nitride spacers of the device are still the source of charge spreading at the edge of the channel.
A need therefore exists for methodology enabling formation of an EDNMOS with nitride spacers pushed away from the edge of the channel and the resulting device.